GALS System Design:
Side Channel Attack Secure Cryptographic Accelerators

Appendices

Frank Kagan Gürkaynak
 
<kgf@ieee.org>

 
Disclaimer:
This is the www enabled version of my thesis. This has been converted from the sources of the original file by using TTH, some perl and some hand editing. There is also a PDF. This is essentially as it is, but includes formatting for A4, and some of the color pictures from the presentation.

Contents

1  Introduction
2  GALS System Design
3  Cryptographic Accelerators
4  Secure AES Implementation Using GALS
5  Designing GALS Systems
6  Conclusion
A  'Guessing' Effort for Keys
B  List of Abbreviations
B  Bibliography
B  Footnotes

Appendix A
'Guessing' Effort for Keys

Most popular accounts that deal with overly large numbers make an effort to describe the large number in quantities that can be more easily visualized. For cryptographic algorithms, the question is usually how much effort is required to guess the correct cipherkey using a brute force attack. It is a lot. Although scientists dealing with theoretical cryptography will tell otherwise, it is practically impossible to succeed in a brute force attack against a good cryptographic algorithm with a cipherkey length exceeding 100 bits.
Table A.1 should help the reader to easily come up with dramatic expressions that describe the amount of time and resources required to find the correct permutation of bits in an n-bit cipherkey. Note that in average 2n-1 attempts are required for guessing the correct cipherkey. Simply choose some quantities and time spans from the table and add up the indicated bits so that the total matches n-1 .
Descriptionbitsvalue
quantities
a million201·106
number of AES encryptions that can be calculated per second using the fastest Pentium processor2420·106
number of processors that can be powered by one nuclear reactor2540·106
number of people living in the world32.56.5·109
number of processors that can be powered by the total amount of energy consumed in the world39500·109
number of floating point operations calculated by the fastest supercomputer of the world each second (as of June 2005) 47136·1012
number of atoms in a drop of water7310·1021
number of processors that can fill all oceans of the world78323·1021
number of processors that can be powered by the sun8416·1024
number of atoms in a human body92.57·1027
number of atoms in planet earth166.5133·1048
time spans
seconds in a year2531.5·106
average life of man in seconds312.4·109
written history in seconds37.5189·1012
age of the world in seconds57145·1015
age of the universe in seconds59630·1015
Table A.1: Some practical examples for large numbers and the equivalent amount of cipherkey bits. Most of the values are approximations found on the Internet and are only for comparison purposes.
As an example for AES-128 (127 bits) the following expression can be derived:
"If everyone living on this world would possess the fastest known computer in the world, guessing one 128-bit cipherkey would take approximately 1000 times longer than the written history of mankind (roughly 6 million years)"

Appendix B
List of Abbreviations

Ack
Acknowledge (signal for GALS systems)
AES
Advanced Encryption Standard
AFSM
Asynchronous Finite State Machine
ASIC
Application Specific Integrated Circuit
AT
Area Time (product)
ATM
Automated Teller Machine
CBC
Cipher Block Chaining Mode
CFB
Cipher Feedback Mode
CMOS
Complementary Metal Oxide Semiconductor
CTR
Counter Mode
DES
Digital Encryption Standard
DI
Delay Insensitive (asynchronous circuit)
DOP
Dummy Operation
DPA
Differential Power Analysis
DVFS
Dynamic Voltage and Frequency Scaling
ECB
Electronic Codebook Mode
EDA
Electronic Design Automation
EEPROM
Electrically Erasable Programmable Read Only Memory
FIFO
First-In First-Out
FIPS
Federal Information Processing Standard
FPGA
Field Programmable Gate Array
GALS
Globally Asynchronous Locally Synchronous
I/O
Input and Output
JTAG
Joint Test Action Group
LFSR
Linear Feedback Shift Register
LS
Locally Synchronous (Island)
MPW
Multi Project Wafer
MutEx
Mutual Exclusion Element
NIST
National Institute of Standards and Technology
NoC
Network on Chip
OFB
Output Feedback Mode
Pen
Port Enable (control signal for GALS systems)
PRNG
Pseudo Random Number Generator
QDI
Quasi Delay Insensitive (asynchronous circuit)
QoS
Quality of Service
RAM
Random Access Memory
Req
Request (signal for GALS systems)
ROM
Read Only Memory
RSA
Rivest, Shamir, Adleman (authors of the public key cryptographic algorithm)
SI
Speed Independent (asynchronous circuit)
SoC
System on Chip
STG
Signal Transition Graph
Ta
Transfer Acknowledge (signal for GALS systems)
TEE
Test Extension Element
UMC
United Microelectronic Corporation


File translated from TEX by TTH, version 3.77.
On 20 Dec 2006, 15:44.