GALS System Design:
Side Channel Attack Secure Cryptographic Accelerators

Bibliography

Frank Kagan Gurkaynak
 
<kgf@ee.ethz.ch>

 
Disclaimer:
This is the www enabled version of my thesis. This has been converted from the sources of the original file by using TTH, some perl and some hand editing. There is also a PDF. This is essentially as it is, but includes formatting for A4, and some of the color pictures from the presentation.

Contents

1  Introduction
2  GALS System Design
3  Cryptographic Accelerators
4  Secure AES Implementation Using GALS
5  Designing GALS Systems
6  Conclusion
A  'Guessing' Effort for Keys
B  List of Abbreviations
B  Bibliography
B  Footnotes

Bibliography

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F. K. Gürkaynak, A. Burg, D. Gasser, F. Hug, N. Felber, H. Kaeslin, and W. Fichtner, A 2Gb/s Balanced AES Crypto-Chip Implementation, Proc. of the Great Lakes Symposium on VLSI, ACM Press, April 2004, pp. 39-44.
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[GOK+05]
Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, and Wolfgang Fichtner, Design Challenges for a Differential Power Analysis Aware GALS based AES Crypto-ASIC, Proceedings of the 2nd Int. Workshop on Formal Methods For Globally Asynchronous Locally Synchronous Architectures FMGALS2005, July 2005.
[GOV03a]
Frank K. Gürkaynak, Stephan Oetiker, and Thomas Villiger, GALS Bus Test Chip: Shir Khan, Technical Report 11/2003, Integrated Systems Laboratory, ETH Zurich, Switzerland, 2003.
[GOV+03b]
Frank K. Gürkaynak, Stephan Oetiker, Thomas Villiger, Norbert Felber, Hubert Kaeslin, and Wolfgang Fichtner, On the GALS Design Methodology of ETH Zurich, Proceedings of the Formal Methods For Globally Asynchronous Locally Synchronous (GALS)Architecture FMGALS2003, September 2003, pp. 181-189.
[GT03]
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[GVO+02]
Frank K. Gürkaynak, Thomas Villiger, Stephan Oetiker, Norbert Felber, Hubert Kaeslin, and Wolfgang Fichtner, A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2002, pp. 181-189.
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[IM02]
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[KB95]
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[KGS05]
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[KJJ99]
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[KL02]
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[KMB03]
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[LTG+02]
A. K. Lutz, J. Treichler, F. K. Gürkaynak, H. Kaeslin, G. Basler, A. Erni, S. Reichmuth, P. Rommens, S. Oetiker, and W. Fichtner, 2 Gb/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis, Proc. Cryptographic Hardware and Embedded Systems - CHES 2002, LNCS 2523, Springer-Verlag, August 2002, pp. 144-158.
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[MM03]
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[MNT+04]
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[MTMR02]
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[MVF00]
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[MvOV96]
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[MZK+99]
Eric Jan Marinissen, Yervant Zorian, Rohit Kapur, Tony Taylor, and Lee Whetsel, Towards a Standard for Embedded Core Test: An Example, Proceedings of the International Test Conference, September 1999, pp. 616 - 627.
[Nat99]
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[Nat01a]


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[Nat01b]


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[NCM+02]
Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop C. Brock, Koji I. Ishii, Tuyet Y. Nguyen, and Jeffrey L. Burns, A 32-bit PowerPC System-on-a-Chip With Support for Dynamic Voltage Scaling and Dynamic Frequency Scaling, IEEE Journal of Solid-State Circuits 37 (2002), no. 11, 1441-2447.
[OGOP04]
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[OGV+03]
Stephan Oetiker, Frank K. Gürkaynak, Thomas Villiger, Hubert Kaeslin, Norbert Felber, and Wolfgang Fichtner, Design Flow for a 3-million Transistor GALS Test Chip, Handouts of the Third Asynchronous Circuit Design Workshop, ACiD 2003, Heraklion, Greece, January 2003.
[OVG+02]
Stephan Oetiker, Thomas Villiger, Frank K. Gürkaynak, Hubert Kaeslin, Norbert Felber, and Wolfgang Fichtner, High Resolution Clock Generators for Globally-Asynchronous Locally-Synchronous Designs, Handouts of the Second ACiD-WG Workshop of the European Commission's Fifth Framework Programme, Munich, Germany, January 2002.
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[PGH+04]
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[SAM+04]
G. Semeraro, D. H. Albonesi, G. Magklis, M. L. Scott, S. G. Dropsho, and S. Dwarkadas, Hiding Synchronization Delays in GALS Processor Microarchitecture, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, April 2004, pp. 159-169.
[SF01]
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[SLHW03]
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[SMBY05]
Danil Sokolov, Julian Murphy, Alex Bystrov, and Alex Yakovlev, Design and Analysis of Dual-Rail Circuits for Security Applications, IEEE Transactions on Computers 54 (2005), no. 4, 449-460.
[Smi04]
Scott F. Smith, An Asynchronous GALS Interface with Applications, In Proc. IEEE Workshop on Microelectronics and Electron Devices, 2004, pp. 41-44.
[SMTM01]
A. Satoh, S. Morioka, K. Takano, and S. Munetoh, A Compact Rijndael Hardware Architecture with S-Box Optimization, Proc. ASIACRYPT 2001, LNCS 2248, Springer-Verlag, 2001, pp. 239-254.
[TV03]
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[Vil05]
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[VSK03]
I. Verbauwhede, P. Schaumont, and H. Kuo, Design and Performance Testing of a 2.29-GB/s Rijndael Processor, IEEE Journal of Solid-State Circuits 38 (2003), no. 3, 569-572.
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[WOL02]
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[YD99b]


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[YFP03]
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File translated from TEX by TTH, version 3.77.
On 20 Dec 2006, 15:44.